1. Field of Invention
The present invention relates to a charge pump and a voltage doubler using the same. More particularly, the present invention relates to a charge pump comprising low-pressure fabricated metal-oxide-semiconductor (MOS) devices and a voltage doubler using the same.
2. Description of Related Art
FIG. 1A is a circuit diagram of a conventional charge pump. As shown in FIG. 1A, the charge pump 10 comprises two N-type metal oxide semiconductor (NMOS) transistors 102 and 104 and two capacitors 112 and 114. One source/drain terminal of the NMOS transistor 102 is electrically coupled to an input voltage VIN terminal while the other source/drain terminal of the NMOS transistor 102 is electrically coupled to one terminal 112a of the capacitor 112. The substrate terminal of the NMOS transistor 102 is connected to ground and the gate terminal of the NMOS transistor 102 is connected to one terminal 114a of the capacitor 114. Voltage at the capacitor terminal 114a serves as an output voltage V01, of the charge pump 10. Similarly, one source/drain terminal of the NMOS transistor 104 is electrically coupled to the input voltage VIN terminal while the other source/drain terminal of the NMOS transistor 104 is electrically coupled to the capacitor terminal 114a. The substrate terminal of the NMOS transistor 104 is connected to ground and the gate terminal of the NMOS transistor 104 is electrically connected to the capacitor terminal 112a. Voltage at the capacitor terminal 112a serves as another output voltage V02 of the charge pump 10. In addition, the other terminal 112b of the capacitor 112 receives a clocking signal CK and the other terminal 114b of the capacitor 114 receives an inverse clocking signal CK′ during operation.
Initially, voltage difference at the two terminals of both capacitors 112 and 114 is at 0V. Assume that the clocking signal CK is a signal having a voltage between 0 to V1 during operation, the voltage V1 is identical or greater than VIN and the clocking signal CK is at a high potential level initially. At the beginning of operation, voltage difference between the ends of the capacitor 112 is maintained at 0V due to the capacitor property. Hence, voltage at the capacitor terminal 112a is raised to V1. Under this condition, because the inverted clocking signal CK′ is at 0V, the charge pump 10 outputs a voltage V01 of 0V and a voltage V02 of V1. Thereafter, since V1≧VIN, the NMOS transistor 104 conducts and hence VIN gradually charges up the capacitor 114. Consequently, after the passage of some time, voltage at the capacitor terminal 114a is raised to a level almost identical to VIN.
When phase of the clocking signal CK reverses back to 0V (that is, phase of the inverted clocking signal CK′ reverses back to V1), voltage difference between the terminals 112a and 112b of the capacitor 112 is maintained during a transient period. Consequently, the capacitor terminal 112a returns to 0V. Similarly, because the voltage difference between the terminals 114a and 114b of the capacitor 114 is maintained during a transient period when phase of the inverted clocking signal CK′ reverses, voltage at the capacitor terminal 114a is pushed up to VIN+V1. In other words, during the transient phase inversion of the clocking signal CK, the output voltage V01 is VIN+V1 and the output voltage V02 is at 0V. Under this condition, the NMOS 104 is cut off and the NMOS transistor 102 conducts because the gate voltage (equivalent to the output voltage V01) is greater than the input voltage VIN. Thus, voltage at the capacitor terminal 112a gradually rises from 0V towards VIN.
For the same reason, during the transient period when the phase of the clocking signal CK reverses, the output voltage V01 drops back to VIN while the output voltage V02 rises up towards VIN+V,. In subsequent operations, the output voltages V01 and V02 will fluctuate in cycles between VIN and VIN+V1.
However, for this type of circuit, the biggest voltage difference sustainable by the gate-substrate of the NMOS transistors 102 and 104 is VIN+V1. Therefore, the NMOS transistors 102 and 104 must be able to withstand a voltage greater than VIN+V1. In other words, the gate-substrate interface of the NMOS transistors 102 and 104 must be able to withstand a voltage difference equivalent to the output voltage value.
A voltage doubler that uses this type of charge pump was first disclosed in the article ‘A High-Efficiency CMOS Voltage Doubler’ of the IEEE Journal of Solid State Circuits, Vol. 33, No. 3, March 1998 by Philippe Deval and Mechel J. Declercq. FIG. 1B is a circuit diagram of the voltage doubler that uses the conventional charge pump design shown in FIG. 1A. The clocking signal CK varies cyclically between VIN and 0V during operation. Hence, the output voltage VOUT approaches 2*VIN. Similarly, the gate-substrate interface of the NMOS transistor 122 and 124 must be able to sustain a voltage difference of at least 2*VIN. In FIG. 1B, a clock signal CK is connected to a terminal 132b of the capacitor 132. The another terminal 132a of the capacitor 132 is connected to the NMOS transistor 122. Similarly, an inverted clock signal CK′ is connected to a terminal 134b of the capacitor 134. The another terminal 134a of the capacitor 134 is connected to the NMOS transistor 124. In addition, the PMOS transistors 140, 142, 144, and 146 form a circuit, as shown in FIG. 1B, which has two terminals coupled to the terminals 132a and 134a and a voltage output terminal VOUT. The voltage output terminal is also coupled to a ground via a capacitor 152. In addition all the substrates of the PMOS transistors 140, 142, 144, and 146 are coupled to the around via a capacitor 150.